This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-073491, filed Mar. 18, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a charge-pumping circuit which produces a boosted voltage. More particularly, this invention pertains to a charge-pumping circuit which is demanded of low power consumption while a device in which the charge-pumping circuit is installed is stopping operation or is in a standby mode.
The microfabrication technology and schemes to reduction in the source voltage have improved the performances of semiconductor devices. Some of the semiconductor devices, such as memories which cannot set the voltage to be applied to memory cells or the like equal to an external voltage, incorporate a voltage boosting circuit or a charge-pumping circuit.
The electric potential boosted inside a chip by the charge-pumping circuit is maintained even when the chip is stopped (inactive or standby mode). This is to assure the chip performances, such as the access time, immediately after the transition from the standby state to the active state.
To hold the boosted potential even in the standby state, the charge-pumping circuit is designed to always monitor the boosted voltage level and automatically restart the charge-pumping operation if the inner potential drops due to leakage or the like in transistors. To achieve this function, the current dissipation of a device which carries out inner voltage boosting does not become zero even in standby mode. (This current will hereinafter be called xe2x80x9cstandby currentxe2x80x9d.)
Recently, it has become typical to incorporate devices which implement inner voltage boosting into portable devices. This naturally makes the demand of reducing the standby current severer. This is because portable devices basically operate on the battery voltage so that even slight current flowing in such a portable device directly affects the performance of the device, such as making the standby time of the device shorter.
Accordingly, the allowed standby current of the charge-pumping circuits becomes smaller than the conventional standby current. The operation of the conventional charge-pumping circuit will now be described specifically from the viewpoint of reducing the standby current.
FIG. 1 is a diagram showing the structure of a typical conventional charge-pumping circuit. The main portion of the conventional charge-pumping circuit shown in FIG. 1 comprises transistors Qi (i: natural number) which has gate-drain common connection and capacitors Ci whose one electrodes are connected to the drains of the respective transistors Qi.
Multiple stages of circuits each comprising the transistor Qi and capacitor Ci are connected in series (i is 1 to 4 in this example) and the capacitor Ci of each stage is driven alternately to an xe2x80x9cHxe2x80x9d (High) level and an xe2x80x9cLxe2x80x9d (Low) level, thereby transferring charges.
Reference symbol xe2x80x9cQinxe2x80x9d denotes an input transistor. The input end of the current path formed by the transistors Qi and the capacitors Ci is connected to an external voltage VDDO. A boosted output voltage VDDR is output from the source of the transistor Q4 of the last stage.
A control system for the conventional charge-pumping circuit as illustrated in FIG. 1 is constructed as follows.
An enable signal ENABLE is supplied to one input terminals of NAND gates NAND1 and NAND2. The output of the NAND gate NAND1 is supplied to the gate of the transistor Qin via an inverter IV1.
The output signal, OSC, of an unillustrated oscillator is supplied to the other input terminal of the NAND gate NAND2. The output of the NAND gate NAND2 is separated into two paths to alternately drive the capacitors Ci. Specifically, the output of the NAND gate NAND2 is supplied to the other electrodes of the capacitors C1 and C3 via inverters IV2, IV3 and IV4 in one path, and is supplied to the other input terminal of the NAND gate NAND1 and the other electrodes of the capacitors C2 and C4 via the inverter IV2 and an inverter IV5 in the other path.
This charge-pumping circuit is activated when the signal ENABLE becomes an xe2x80x9cHxe2x80x9d level. When the signal ENABLE becomes the xe2x80x9cHxe2x80x9d level, the output of the NAND gate NAND2 transfers the output signal OSC (xe2x80x9cHxe2x80x9d/xe2x80x9cLxe2x80x9d level) of the oscillator. The output of the NAND gate NAND1 transfers the output of the inverter IV5 via the inverter IV1, so that a timing signal of an xe2x80x9cHxe2x80x9d/xe2x80x9cLxe2x80x9d level is supplied to the gate of the transistor Qin.
The individual capacitors Ci which are connected to nodes adjoining with the associated transistor Qi for charge transfer in between are driven to different levels of xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d. This allows charges to be transferred from one transistor to another so that the boosted output voltage VDDR is acquired from the transistor Q4 of the last stage.
From the viewpoint of charge transfer, it is desirable that the threshold voltage of the transistors Qi having diode connection be as close to 0V as possible. To meet this requirement, intrinsic transistors (I-type transistors) which are fabricated without making channel ion implantation in the substrate are used for the transistors (Qin and Qi) that constitute a charge-pumping circuit. Because the I-type transistor on the substrate has a low impurity concentration at the channel portion, the threshold voltage of that transistor can be set to approximately 0V.
FIG. 2A is a circuit diagram depicting individual potential nodes of an I-type transistor having diode connection formed on a substrate. FIG. 2B is a diagram illustrating characteristic curves of the drain current ID versus drain voltage VD of the I-type transistor under the conditions shown in FIG. 2A.
A substrate potential VB is the ground potential (VB=0V). The log scale (the scale on the left-hand side of the graph) will mainly be referred to when the drain voltage VD is lower than the source voltage VS (equal to the gate voltage VG), and the linear scale (the scale on the right-hand side of the graph) will mainly be referred to when the drain voltage VD is higher than the source voltage VS (equal to the gate voltage VG).
FIG. 3A is a circuit diagram depicting individual potential nodes of another I-type transistor formed on a substrate. FIG. 3B is a diagram illustrating characteristic curves of the drain current ID versus gate voltage VG of the I-type transistor under the conditions shown in FIG. 3A. As indicated by arrows in FIG. 3B, the log scale on the left-hand side will be referred to for the upper curves and the linear scale on the right-hand side will be referred to for the lower curves.
FIG. 4A is a circuit diagram depicting individual potential nodes of an I-type transistor formed on a substrate. FIG. 4B is a diagram illustrating characteristic curves of the drain current ID versus gate voltage VG under the conditions shown in FIG. 4A. As likewise indicated by arrows in FIG. 4B, the log scale on the left-hand side will be referred to for the upper curves and the linear scale on the right-hand side will be referred to for the lower curves.
Attention is paid to the states of the individual nodes in the charge-pumping circuit shown in FIG. 1 when the charge-pumping circuit becomes the standby state from the active state to stop the charge-pumping operation.
In general, in the standby state where the charge-pumping operation is stopped, the signal ENABLE becomes the xe2x80x9cLxe2x80x9d level, forcibly inhibiting the supply of the output signal OSC of the oscillator. That is, nodes N1 to N4 of the capacitors of the individual stages are disabled while having the alternate xe2x80x9cHxe2x80x9d level and xe2x80x9cLxe2x80x9d level.
As shown in FIGS. 2A and 2B, even when the backward bias is applied to the transistors Qi of the individual stages that have diode connection, the transistors Qi do not go into a cut-off state. With the drain voltage VD being 10V, particularly, a current of about 20 xcexcA flows when the source voltage VS (VG) is 1V.
As shown in FIGS. 3B and 4B, the I-type transistor has a negative threshold voltage, so that even when the gate voltage becomes negative, this transistor will not be turned off and a slight current keeps flowing. That is, the instance the charge-pumping circuit shown in FIG. 1 stops, the reverse charge flow occurs through the transistors Qi of the individual stages. The greater the difference between the driving voltage (VDDO) of the charge-pumping circuit and the boosted output voltage (VDDR) becomes, the larger the amount of the reverse-flowing charges gets.
If the reverse-flowing charges decrease the level of the voltage boosted node, the charge-pumping circuit should operate to supplement the potential as mentioned above.
In other words, the presence of the reverse-flowing charges in the charge-pumping circuit is one factor to increase the standby current and the amount of the reverse-flowing charges increases as the level difference between the external voltage and the boosted potential becomes greater. It is therefore extremely difficult to meet both of the recent requirements of reducing the external voltage and reducing the standby current.
To improve the cut-off characteristic of transistors to such a degree that the reverse-flowing charges become negligible, the value of the gate voltage VG corresponding to ID=10xe2x88x929 A in FIG. 4B should be shifted above VG=0V. This means that the improvement cannot be achieved unless the threshold voltage Vth of the transistors is set to is equal to or higher than +0.5V.
If the threshold voltage Vth of transistors is increased by channel ion implantation or the like as mentioned above, however, the back bias effect increases, thus significantly deteriorating the current supplying capability in the charge-pumping operation. This necessitates the use of I-type transistors at present.
The problem that the conventional charge-pumping circuit shown in FIG. 1 has at the time it changes to the active state from the standby state will now be discussed by using the results of simulation of the initial characteristics of the charge-pumping operation shown in FIGS. 5A and 5B.
FIG. 5A presents a characteristic diagram illustrating the transition of the charge-pumping circuit until the capacitor nodes are restored to the stable level where they have the alternate xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels when the charge-pumping circuit is reactivated. FIG. 5B presents a characteristic diagram illustrating the transition of the charge-pumping circuit until the stable current supply is resumed when the charge-pumping circuit is reactivated.
As each capacitor node is not at the proper level due to the reverse charge flow from the boosted voltage level as indicated by an arrow-headed period A along the time axis in FIGS. 5A and 5B, it takes time to achieve the alternate xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels at the time the operation returns to the active state from the standby state. This means that it takes time for the charge-pumping circuit to output the maximum current.
Unless the effective period A of the charge-pumping operation in which the charge-pumping circuit goes to the active state from the standby state can be shortened, the charge-pumping operation cannot supplement the boosted current consumed in the chip immediately after the charge-pumping circuit becomes active. This disables the assurance of the chip performances such as the access time.
The problems of the conventional charge-pumping circuit will be summarized below.
As mentioned above, the instance the conventional charge-pumping circuit stops, the reverse flow of charges to be transferred to the capacitors Ci via the transistors Qi of the individual stages occurs and it cannot be reduced as long as I-type transistors are used as the transistors Qi of the individual stages.
Because the conventional charge-pumping circuit has to operate to supplement the potential if the reverse charge flow reduces the level of the voltage boosted node in standby mode, the current dissipation increases inevitably.
As each capacitor node in the charge-pumping circuit is not at the proper level due to the reverse charge flow from the boosted voltage level, it takes time to resume the stable current supply when the charge-pumping circuit is reactivated.
Accordingly, it is an object of the present invention to provide a charge-pumping circuit which uses I-type transistors and has a control system that can suppress the reverse charge flow in standby mode.
That is, this invention aims at providing a charge-pumping circuit having a control system that can reduce the current dissipation when the charge-pumping operation is stopped (when an associated device is in standby mode) and can shorten the time for the output current acquired provided the charge-pumping operation to reach the maximum value when the charge-pumping circuit is reactivated.
To achieve the above object, according to one aspect of this invention, there is provided a charge-pumping circuit comprising a circuit including plural stages of circuit portions connected in series, each circuit portion having a transistor having a drain and gate connected together and a capacitor having a connection node at which one electrode of the capacitor is connected to the drain of the transistor in such a way that driving potentials to be applied to adjoining connection nodes of individual capacitors alternately become a high level and a low level when the charge-pumping circuit is in operation, wherein when the charge-pumping circuit stops operating, the driving potentials of the connection nodes of the individual capacitors are all fixed to a same level close to an output level of the charge-pumping circuit.
The charge-pumping circuit receives an external source voltage as input voltage and outputs a boosted voltage in a power source circuit to be used in at least one of writing, reading and erasing storage data in a memory cell array of a semiconductor memory device based on internal control signals of the semiconductor memory device, and the boosted voltage being input to at least one of a row decoder, a column decoder and a source/well decoder of the memory cell array.
According to this invention, all of the driving potentials of the capacitors are set to the same level close to the output level of the charge-pumping circuit when the charge-pumping operation is stopped, it is possible to minimize the loss of the inner boosted potential caused by the reverse current from transistors which have gate-drain common connection and are connected to the respective stages. It is also possible to at least assure the difference between the capacitor driving voltages at the individual stages at the initial stage of the charge-pumping operation.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.